1. Field of the Invention
This invention relates to a semiconductor device having a semiconductor substrate with a double well structure in which two wells different in conductivity from each other are formed within the semiconductor substrate and a method of manufacturing the semiconductor device.
2. Description of the Related Art
The following semiconductor substrate may be used to manufacture a semiconductor memory device including a non-volatile semiconductor element such as an EP-ROM (Erasable and Electrically Programmable Read Only Memory) or an EEP-ROM (Electrically-Erasable Programmable Read Only Memory), or a CMOS (Complementary Metal-Oxide Semiconductor). This type of semiconductor substrate has a first well portion and a second well portion. The first well portion is exposed onto the surface of the semiconductor substrate and different in conductivity from the substrate. The second well portion is formed so as to be bared on the surface of the semiconductor substrate in the first well portion and is identical in conductivity to the substrate.
The semiconductor substrate having such a double well structure includes the following forming process. The first well portion is formed by injecting impurity ions into the semiconductor substrate. Further, ions (hereinafter called "channel stop ions") for forming channel stop regions are injected into a field insulating film forming region excluding the first well portion of the substrate. After the formation of field insulating films, the second well portion is formed within the first well portion by the injection of the impurity ions.
The second well portion has a plurality of active regions. These active regions are used as a memory array region portion for a non-volatile storage element and a peripheral element region portion for circuits around the non-volatile storage element.
The impurity ions, which have been injected to form the second well portion, were considered to have ensured a source-to-drain withstand voltage property of each of transistors formed within the peripheral element region portion. Therefore, the channel stop ions have been injected only into the memory array region portion after the formation of the second well portion.